View LT1394-15_8979598.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 lt1394 7ns, low power, single supply, ground-sensing comparator n high speed a/d converters n zero-crossing detectors n current sense for switching regulators n extended range v/f coverters n fast pulse height/width discriminators n high speed triggers n line receivers n high speed sampling circuits propagation delay vs input overdrive overdrive (mv) 0 time (ns) 12 10 8 6 4 2 0 10 20 30 40 1394 ta02 50 t pdlh t pdhl t a = 25 c v step = 100mv v s = 5v , ltc and lt are registered trademarks of linear technology corporation. ultrafast is a trademark of linear technology corporation. n ultrafast tm : 7ns n low power: 6ma n low offset voltage: 0.8mv n operates off single 5v or dual 5v supplies n input common mode extends to negative supply n no minimum input slew rate requirement n complementary ttl outputs n inputs can exceed supplies without phase reversal n pin compatible with lt1016, lt1116 and lt1671 n output latch capability n available in 8-lead msop and so packages the lt ? 1394 is an ultrafast (7ns) comparator with comple- mentary outputs and latch. the input common mode range extends from 1.5v below the positive supply down to the negative supply rail. like the lt1016, lt1116 and lt1671, this comparator has complementary outputs designed to interface directly to ttl or cmos logic. the lt1394 may operate from either a single 5v supply or dual 5v supplies. low offset voltage specifications and high gain allow the lt1394 to be used in precision applications. the lt1394 is designed for improved speed and stability for a wide range of operating conditions. the output stage provides active drive in both directions for maximum speed into ttl, cmos or passive loads with minimal cross-conduc- tion current. unlike other fast comparators, the lt1394 remains stable even for slow transitions through the active region, which eliminates the need to specify a minimum input slew rate. the lt1394 has an internal, ttl/cmos compatible latch for retaining data at the outputs. the latch holds data as long as the latch pin is held high. device parameters such as gain, offset and negative power supply current are not significantly affected by variations in negative supply voltage. 45mhz single supply adaptive trigger 5v + a1 lt1227 + a2 lt1006 input 5v 5v 5v trigger out 1394 f18 500pf 0.1 f 510 470 470 750 36 1 3 2 4 14 13 15 5 6 12 10 11 2k 10 f 2k 2k + 0.1 f 0.1 f 0.005 f 0.005 f 100 f + q1, q2, q3, q4 = ca3096 array: tie substrate (pin 16) to ground = 1n4148 + lt1394 q1 q2 q3 q4 3m 3m features descriptio u applicatio s u typical applicatio u
2 lt1394 absolute m axi m u m ratings w ww u t jmax = 150 c, q ja = 190 c/ w top view q out q out gnd v + +in ?n v s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 + latch enable order part number s8 part marking lt1394cs8 lt1394is8 1394 1394i package/order i n for m atio n w u u (note 1) total supply voltage (v + to v C ) ............................... 12v positive supply voltage ............................................. 7v negative supply voltage .......................................... C 7v differential input voltage ....................................... 12v input and latch current (note 2) ........................ 10ma output current (continuous)(note 2) ................. 20ma consult factory for military grade parts. electrical characteristics symbol parameter conditions min typ max units v os input offset voltage r s 100 w (note 4) 0.8 2.5 mv l 4.0 mv d v os input offset voltage drift l 4 m v/ c d t i os input offset current 0.1 0.5 m a l 0.8 m a i b input bias current (note 5) 2 4.5 m a l 7.0 m a v cmr input voltage range (note 6) l C 5 3.5 v single 5v supply l 0 3.5 v cmrr common mode rejection ratio C 5v v cm 3.5v, t a > 0 c 55 100 db C5v v cm 3.3v, t a 0 c55 db single 5v supply 0v v cm 3.5v, t a > 0 c 55 100 db 0v v cm 3.3v, t a 0 c55 db psrr power supply rejection ratio 4.6v v + 5.4v l 50 65 db C7v v C C2v l 65 100 db a v small signal voltage gain 1v v out 2v 750 1600 v/v v oh output voltage swing high v + 3 4.6v, i out = 1ma l 2.7 3.1 v v + 3 4.6v, i out = 4ma l 2.4 3.0 v operating temperature range ................ C 40 c to 85 c specified temperature range (note 3) ... C 40 c to 85 c junction temperature ........................................... 150 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c 1 2 3 4 v + +in ?n v 8 7 6 5 q out q out gnd top view ms8 package 8-lead plastic msop latch enable t jmax = 150 c, q ja = 250 c/ w order part number ms8 part marking lt1394cms8 ltbh the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v + = 5v, v C = C 5v, v out (q) = 1.4v, v latch = v cm = 0v unless otherwise noted.
3 lt1394 electrical characteristics symbol parameter conditions min typ max units v ol output voltage swing low i out = C 4ma l 0.3 0.5 v i out = C 10ma 0.4 v i + positive supply current 6 8.5 ma l 10.0 ma i C negative supply current 1.2 2.2 ma l 2.5 ma v ih latch pin high input voltage l 2v v il latch pin low input voltage l 0.8 v i il latch pin current v latch = 0v l C4 C10 m a t pd propagation delay (note 7) d v in = 100mv, v od = 5mv 7 9 ns l 14 ns d t pd differential propagation delay (note 7) d v in = 100mv, v od = 5mv 0.5 2.2 ns t lpd latch propagation delay (note 8) 6 ns t su latch setup time (note 8) C 0.4 ns t h latch hold time (note 8) 2ns t pw(d) minimum disable pulse width 3ns note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: this parameter is guaranteed to meet specified perforamnce through design and characterization. it has not been tested. note 3: the lt1394cms8 and lt1394cs8 are guaranteed to meet specified performance from 0 c to 70 c and are designed, characterized and expected to meet these extended temperature limits, but are not tested at C 40 c and 85 c. the lt1394is8 is guaranteed to meet the extended temperature limits. note 4: input offset voltage (v os ) is defined as the average of the two voltages measured by forcing first one output, then the other to 1.4v. note 5: input bias current (i b ) is defined as the average of the two input currents. note 6: input voltage range is guaranteed in part by cmrr testing and in part by design and characterization. note 7: t pd and d t pd cannot be measured in automatic handling equipment with low values of overdrive. the lt1394 is 100% tested with a 100mv step and 20mv overdrive. correlation tests have shown that t pd and d t pd limits can be guaranteed with this test, if additional dc tests are performed to guarantee that all internal bias conditions are correct. propagation delay (t pd ) is measured with the overdrive added to the actual v os . differential propagation delay is defined as: d t pd = t pdlh C t pdhl note 8: latch propagation delay (t lpd ) is the delay time for the output to respond when the latch pin is deasserted. latch setup time (t su ) is the interval in which the input signal must remain stable prior to asserting the latch signal. latch hold time (t h ) is the interval after the latch is asserted in which the input signal must remain stable. the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v + = 5v, v C = C 5v, v out (q) = 1.4v, v latch = v cm = 0v unless otherwise noted.
4 lt1394 typical perfor m a n ce characteristics u w propagation delay vs input overdrive temperature ( c) ?0 time (ns) 12 10 8 6 4 2 0 25 75 1394 g05 ?5 0 50 100 125 v s = 5v v step = 100mv v od = 5mv t pdlh t pdhl source resistance (k ) 0 0.5 time (ns) 1.0 2.0 1.5 2.5 3.0 1394 g04 80 70 60 50 40 30 20 10 0 v s = 5v v od = 20mv t a = 25 c step size = 800mv 400mv 100mv 200mv propagation delay vs source resistance propagation delay vs temperature input offset voltage vs temperature 2 1 0 ? ? ? ? ? lt 1394 g06 voltage (mv) temperature ( c) ?0 25 75 ?5 0 50 100 125 v s = 5v 4 3 2 1 0 lt 1394 g07 input bias current ( a) temperature ( c) ?0 25 75 ?5 0 50 100 125 v s = 5v v cm = 5v v cm = 0v v cm = 3.5v input bias current vs temperature temperature ( c) ?0 voltage (v) 6 5 4 3 2 1 0 25 75 1394 g08 ?5 0 50 100 125 v s = 5v positive common mode limit vs temperature overdrive (mv) 0 time (ns) 12 10 8 6 4 2 0 10 20 30 40 1394 ta02 50 t pdlh t pdhl t a = 25 c v step = 100mv v s = 5v gain characteristics positive supply voltage (v) 4.4 time (ns) 12 10 8 6 4 2 0 4.6 4.8 5.0 5.2 5.4 1394 g03 5.6 t pdhl t pdlh v = 5v t a = 25 c v step = 100mv overdrive = 5mv propagation delay vs positive supply voltage propagation delay vs load capacitance output load capacitance (pf) 0 time (ns) 12 10 8 6 4 2 0 10 20 30 40 1394 g02 50 t pdlh t pdhl i out = 0 v s = 5v t a = 25 c v step = 100mv overdrive = 5mv differential input voltage (mv) ? output voltage (v) ? ? 01 1394 g01 2 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3 v s = 5v i out = 0 t a = 125 c t a = 25 c t a = 55 c
5 lt1394 output high voltage (v oh ) vs output source current negative common mode limit vs temperature 1 0 ? ? ? ? ? ? lt 1394 g09 input voltage (v) temperature ( c) ?0 25 75 ?5 0 50 100 125 v s = 5v v s = single 5v output sink current (ma) 02 6 10 14 voltage (v) 16 1394 g10 4 8 12 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 t a = 55 c t a = 125 c t a = 25 c v s = 5v ? v in = 30mv output low voltage (v ol ) vs output sink current output source current (ma) 02 6 10 14 output voltage (v) 16 1394 g11 4 8 12 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 t a = 55 c t a = 125 c t a = 25 c v s = 5v ? v in = 30mv typical perfor m a n ce characteristics u w supply voltage (v) 0 current (ma) 10 9 8 7 6 5 4 3 2 1 0 2 4 5 1394 g12 13 6 7 8 t a = 55 c t a = 125 c v = 0v v in = 60mv i out = 0 t a = 25 c switching frequency (mhz) 1 current (ma) 16 14 12 10 8 6 4 2 0 10 100 1394 g13 t a = 55 c t a = 125 c v s = 5v t a = 25 c positive supply current vs v + supply voltage positive supply current vs switching frequency negative supply voltage (v) ? current (ma) 0 1394 g14 ? ? ? 4 3 2 1 0 ? ? ? ? t a = 55 c t a = 125 c t a = 25 c v + = 5v ? v in = 60mv 8 7 6 5 4 3 2 1 0 lt 1394 g15 current ( a) temperature ( c) ?0 25 75 ?5 0 50 100 125 v s = 5v v latch = 0v latch pin current vs temperature negative supply current vs v C supply voltage response to 100mhz 10mv sine wave 0v q out 3v fet probes 5ns/div 1394 g16 +in 20mv p-p 10mv/div 1v/div
6 lt1394 pi n fu n ctio n s uuu v + (pin 1): positive supply voltage. normally 5v. +in (pin 2): noninverting input. Cin (pin 3): inverting input. v C (pin 4): negative supply voltage. normally either 0v or C 5v. latch enable (pin 5): latch control pin. when high, the outputs remain in a latched condition, independent of the current state of the inputs. gnd (pin 6): ground. q out (pin 7): noninverting logic output. this pin is high when +in is above Cin and latch enable is low. q out (pin 8): inverting logic output. this pin is low when +in is above Cin and latch enable is low. ti i g diagra s u w w v out v in d v in v od t pd 1394 td01 v out latch enable t h t su t l pd 1394 td02 v in typical perfor m a n ce characteristics u w t pd + response time to 5mv overdrive C95mv 5mv v s = 5v 2ns/div f in = 2mhz v od = 5mv 1394 g17 t pd C response time to 5mv overdrive +in q out q out C95mv 5mv +in 1.4v 0v 1.4v 0v v s = 5v 2ns/div f in = 2mhz v od = 5mv 1394 g18
7 lt1394 applicatio n s i n for m atio n wu u u common mode considerations the lt1394 is specified for a common mode range of C 5v to 3.5v on a 5v supply or a common mode range of 0v to 3.5v on a single 5v supply. a more general consider- ation is that the common mode range is 0v below the negative supply and 1.5v below the positive supply, inde- pendent of the actual supply voltage. the criterion for common mode limit is that the output still responds correctly to a small differential input signal. when either input signal falls below the negative common mode limit, the internal pn diode formed with the sub- strate can turn on, resulting in significant current flow through the die. an external schottky clamp diode between the input and the negative rail can speed up recovery from negative overdrive by preventing the sub- strate diode from turning on. the zero-crossing detector in figure 1 demonstrates the use of a fast clamp diode. the zero-crossing detector terminates the transmission line at its 50 w characteristic impedance. negative inputs should not fall below C 2v to keep the signal current within the clamp diodes maximum forward rating. positive inputs should not exceed the devices absolute maximum ratings or the power rating on the terminating resistor. either input may go above the positive common mode limit without damaging the comparator. the upper voltage limit is determined by an internal diode from each input to the positive supply. the input may go above the positive supply as long as it does not go far enough above it to conduct more than 10ma. functionality will continue if the remaining input stays within the allowed common mode range. there will, however, be an increase in propagation delay as the input signal switches back into the common mode range. figure 1. fast zero-crossing detector input bias current input bias current is measured with the output held at 1.4v. as with any pnp differential input stage, the lt1394 bias current flows out of the device. it will go to zero on an input which is high and double on an input which is low. latch pin dynamics the latch pin is intended to retain input data (output latched) when the latch pin goes high. the pin will float to a high state when disconnected, so a flow-through condition requires that the latch pin be grounded. the latch pin is designed to be driven with either a ttl or cmos output. it has no built-in hysteresis. to guarantee data retention, the input signal must remain valid at least 2ns after the latch goes high (hold time), and must be valid at least C 0.4ns before the latch goes high (setup time). the negative setup time simply means that the data arriving 0.4ns after (rather than before) the latch signal is valid. when the latch signal goes low, new data will appear at the output in approximately 6ns (latch propagation delay). measuring response time to properly measure the response of the lt1394 requires an input signal source with very fast rise times and exceptionally clean settling characteristics. the last requirement comes about because the standard compara- tor test calls for an input step size that is large compared to the overdrive amplitude. typical test conditions are 100mv step size with 5mv overdrive. this requires an input signal that settles to within 1% (1mv) of final value in only a few nanoseconds with no ringing or settling tail. ordinary high speed pulse generators are not capable of generating such a signal, and in any case, no ordinary oscilloscope is capable of displaying the waveform to check its fidelity. some means must be used to inherently generate a fast, clean edge with known final value. the circuit shown in figure 2 is the best electronic means of generating a fast, clean step to test comparators. it uses a very fast transistor in a common base configuration. the transistor is switched off with a fast edge from the genera- tor and the collector voltage settles to exactly 0v in just a few nanoseconds. the most important feature of this 1394 f01 5v + lt1394 q q cable r t 50 v in r s 50 1n5712
8 lt1394 + lt1394 1394 f02 fet probe fet probe * total lead length including device pin. socket and capacitor leads should be less than 0.5 in. use ground plane ** (v os + overdrive)/200 25 25 5v 0.01 f* 0.01 f 10k 50 v1** 2n3866 0v ?v ?v ?v 50 pulse in 750 400 0.1 f 130 0v 100mv q q applicatio n s i n for m atio n wu u u figure 2. response time test circuit circuit is the lack of feedthrough from the generator to the comparator input. this prevents overshoot on the com- parator input, which would give a false fast reading on comparator response time. to adjust the circuit for exactly 5mv overdrive, v1 is adjusted so that the lt1394 output under test settles to 1.4v (in the linear region). then v1 is changed by C 1v to set overdrive to 5mv. high speed design techniques a substantial amount of design effort has made the lt1394 relatively easy to use. it is much less prone to oscillation than some slower comparators, even with slow input signals. however, as with any high speed comparator, there are a number of pitfalls which may arise because of pc board layout and design. the most common problems involve power supply bypassing. bypassing is necessary to maintain low supply impedance. dc resistance and inductance in supply wires and pc traces can quickly build up to unacceptable levels. this allows the supply line to move with changing internal current levels of the con- nected devices. this will almost always result in improper operation. in addition, adjacent devices connected through an unbypassed supply can interact with each other through the finite supply impedances. bypass capacitors furnish a simple solution to this problem by providing a local reservoir of energy at the device, keeping supply imped- ances low. bypass capacitors should be as close as possible to the lt1394. a good high frequency capacitor such as a 0.1 m f ceramic is recommended, in parallel with a larger capaci- tor such as a 4.7 m f tantalum. poor trace routes and high source impedances are also common sources of problems. be sure to keep trace lengths as short as possible, and avoid running any output trace adjacent to an input trace to prevent unnecessary coupling. if output traces are longer than a few inches, be sure to terminate them with a resistor to eliminate any reflections that may occur. resistor values are typically 250 w to 400 w . also, be sure to keep source impedances as low as possible, preferably 1k w or less. crystal oscillators figure 3s circuits are crystal oscillators. in the circuit (a) the resistors at the lt1394s positive input set a dc bias point. the 2k-0.068 m f path sets up phase shifted feedback and the circuit looks like a wideband unity-gain follower at dc. the crystals path provides resonant positive feed- back and stable oscillation occurs. the circuit (b) is similar, but supports oscillation frequencies to 30mhz. above 10mhz, at-cut crystals operate in overtone mode. because of this, oscillation can occur at multiples of the desired frequency. the damper network rolls off gain at high frequency, ensuring proper operation. switchable output crystal oscillator figure 4 permits crystals to be electronically switched by logic commands. this circuit is similar to the previous examples, except that oscillation is only possible when one of the logic inputs is biased high.
9 lt1394 applicatio n s i n for m atio n wu u u temperature-compensated crystal oscillator (txco) figure 5 is a temperature-compensated crystal oscillator (txco). this circuit reduces oscillator temperature drift by inserting a temperature-dependent compensatory cor- rection into the crystals frequency trimming network. this open-loop correction technique relies on cancellation of the temperature characteristics of the oscillator, which are quite repeatable. the lt1394 and associated components form the crystal oscillator, operating similarly to figure 3s examples. the lm134, a temperature-dependent current source, biases a1. a1 takes gain referred to the lm134s output and the negative offset supplied via the 470k w -lt1004 reference path. note that the lt1004s negative voltage bias is bootstrapped from the oscillators output, maintaining single supply operation. this arrangement delivers tem- perature-dependent bias to the varactor diode, causing a scaled variation in the crystals resonance versus ambient temperature. the varactors bias-dependent capacitance shift pulls crystal frequency to complement the circuits temperature drift. the simple first order fit provided by the compensation is very effective. figure 6 shows results. the C70ppm frequency shift over 0 c to 70 c is corrected within a few ppm. the freq set trim also biases the varactor, allowing accurate output frequency setting. it is worth noting that better compensation is possible by including higher order terms in the temperature-to-volt- age conversion. 18ns, 500 m v sensitivity comparator the ultimate limitation on comparator sensitivity is avail- able gain. unfortunately, increasing gain invariably involves giving up speed. the gain vs. speed trade-off in a fast comparator is usually a practical compromise designed to satisfy most applications. some situations, however, require more sensitivity (e.g., higher gain) with minimal impact on speed. figure 7s circuit adds a differ- ential preamplifier ahead of the lt1394, increasing gain. this permits 500 m v comparisons in 18ns. a parallel path dc stabilization approach eliminates preamplifier drift as an error source. a1 is the differential preamplifier, operat- ing at a gain of 100. its output is ac-coupled to the lt1394. figure 3. crystal oscillators for outputs to 30mhz. circuit (b)s damper network supresses overtone crystals harmonic modes + lt1394 2k 5v 2k 1mhz to 10mhz crystal (at-cut) 0.068 m f output 1394 f03 2k + lt1394 2k 5v 2k 2k 10mhz to 25mhz crystal (at-cut) 200pf output 820pf 22 (a) (b) 1394 f04 + lt1394 1k 5v 1k 1k 75pf d1 output b a logic inputs as many stages as desired xtal a 1k r x xtal b xtal x d2 d x 2k = 1n4148 ground xtal cases figure 4. switchable output crystal oscillator. biasing a or b high places associated crystal in feedback path. additional crystal branches are permissible
10 lt1394 temperature ( c) 0 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 30 50 1394 f06 10 20 40 60 70 frequency deviation (ppm) compensated 0.05ppm/ c uncompensated (varactor correction disabled) 1ppm/ c figure 6. figure 5s compensated vs uncompensated temperature dependence. first order compensation reduces oscillator drift to 0.05ppm/ c + a2 1/2 lt1126 + 5v 5v 200pf output 1394 f07 +input input ?v ?v 1 m f 1 m f 200pf 2k 1k 1k 2k 10k 10k 200 w + a1 lm733 a = 100 + lt1394 a3 1/2 lt1126 + figure 7. parallel preamplified paths allow 18ns comparator response to 500 m v overdrive applicatio n s i n for m atio n wu u u figure 5. temperature-compensated 10mhz crystal oscillator. temperature-dependent varactor bias reduces drift by 20:1 1394 f05 + lt1394 + a1 lt1077 50k 5v 10m 390 0.01 f 1 f 0.068 f 10mv/ c 10mhz 0.05ppm/ c xtal at-cut, 35 25 angle * 1% film resistor lm134 5v freq set lt1004-1.2 bat-85 10mhz 1m* 1m* 5.8m* mv-209 varactor diode 2m 2k 0.01 f 1 f 2m 2k 4.7k 100k 1m 470k* 10k* + 226 *
11 lt1394 applicatio n s i n for m atio n wu u u correct, amplified composite signal at the lt1394s posi- tive input in trace d. the lt1394s output is trace e. figure 9 details circuit propagation delay. the output responds in 18ns to a 500 m v overdrive on a 1mv step. figure 10 plots response time versus overdrive. as might be expected, propagation delay decreases at higher overdrives. a1s noise limits usable sensitivity. a1 has poorly defined dc characteristics, necessitating some form of dc correction. a2 and a3, operating at a differential gain of 100, provide this function. they differ- entially sense a band limited version of a1s inputs and feed dc and low frequency amplified information to the com- parator. the low frequency roll-off of a1s signal path complements a2-a3s high frequency roll-off. the sum- mation of these two signal channels at the lt1394 inputs results in flat response from dc to high frequency. figure 8 shows waveforms for the high gain comparator. trace a is a 500 m v overdrive on a 1mv step applied to the circuits positive input (negative input grounded). trace b shows the resulting amplified step at a1s positive output. trace c is a2s band limited output. a1s wideband output combines with a2s dc corrected information to yield the 5 m s/div 1394 f08 a = 1mv/div 10ns/div 1394 f09 a = 1mv/div b = 1v/div b = 0.1v/div (ac-coupled) c = 0.1v/div d = 0.1v/div e = 5v/div figure 8. 500 m v input (trace a) is split into wideband and low frequency gain paths (traces b and c) and recombined (trace d). comparator output is trace e figure 9. parallel path comparator shows 18ns response (trace b) to 500 m v overdrive (trace a) response time (ns) 15 overdrive ( v) 1100 1000 900 800 700 600 500 16 17 18 1394 f10 figure 10. response time vs overdrive for the composite comparator voltage-controlled delay the ability to set a precise, predictable delay has broad application in pulse circuitry. figure 11s configuration sets a 0 to 300ns delay from a corresponding 0v to 3v control voltage. it takes advantage of the lt1394s speed and the clean dynamics of an emitter switched current source. q1 and q2 form a current source that charges the 1000pf capacitor. when the trigger input is high (trace a, figure 12) both q3 and q4 are on. the current source is off and q2s collector (trace b) is at ground. the latch input at the lt1394 prevents it from responding and its output remains high. when the trigger input goes low, the lt1394s latch input is disabled and its output drops low. q4s collector (trace c) lifts and q2 comes on, delivering constant current to the 1000pf capacitor (trace b). the resulting linear ramp at the lt1394s positive input is compared to the delay programming voltage input. when a crossing occurs, the comparator goes high (trace d). the length of time the comparator was low is directly proportional to the
12 lt1394 figure 12. voltage-controlled delays waveforms. programming voltage determines delay between input (trace a) falling edge and output (trace d) rising edge. high linearity timing ramp (trace b) permits 1ns accuracy and 100ps repeatability 10ns/div 1394 f13 figure 13. high speed expansion of figure 12. ramp (trace b) begins when trigger (trace a) falls and current source turns on (trace c). trace d is output 10ns/div 1394 f14 b = 1v/div c = 0.1v/div d = 1v/div a = 1v/div figure 14. delays output switching begins with trigger falling low (trace a). ramp (trace c) starts 3ns after current source turn-on (trace d). output (trace b) begins 4ns later c = 5v/div d = 5v/div b = 2v/div a = 5v/div 100ns/div 1394 f12 a = 2v/div b = 0.1v/div c = 2v/div d = 2v/div applicatio n s i n for m atio n wu u u delay programming voltage. the fast switching and ramp linearity permits 1ns accuracy and 100ps repeatability. figure 13, a high speed expansion of the current source turn-on, details the clean switching. q4 goes off within 2ns of the trigger input (trace a) dropping low, enabling the current source (q2s emitter is trace c). concurrently, the 1000pf capacitors ramp (trace b) begins. the lt1394s output (trace d) drops low about 7ns later, returning high after crossing (in this case) a relatively low programming voltage. figure 14 juxtaposes the waveforms differently, permitting enhanced study of circuit timing. switching begins with the input trigger falling low (trace a). the ramp (trace c) begins 3ns after the current source turns on (q2 emitter is trace d). the output pulse (trace b) begins about 4ns later. to calibrate this circuit apply a trigger input and 3v to the programming input. adjust the 100 w trim for a 300ns width at the lt1394s output. + lt1394 5v 0.1 f 1394 f11 delay programming voltage input 0v to 3v = 0 to 300ns delay 1000pf trigger input 200ns minimum 1k 330 330 100 lt1634 pnp = 2n5087 npn = 2n2369 220 100 (delay calib) 51pf 0.1 f q1 q2 q output q output q4 q3 figure 11. fast, precise, voltage-controlled delay. emitter switched current source has clean, predictable dynamics
13 lt1394 fast, high impedance, variable threshold trigger a frequent requirement in instrumentation is a fast trigger with a variable threshold. often, a high impedance input is also required. figure 15 meets these requirements. com- parator c1 is the basic trigger, with threshold voltage set at its negative input. source follower q1 provides high impedance with about 2pf input capacitance and 50pa bias current. normally, q1s source bias point would be uncer- tain and drifty, but stabilization techniques eliminate this concern. a1 measures filtered versions of q1s gate and source voltages. a1s output biases q2, forcing q1s channel current to whatever value is required to equalize a1s inputs, and hence q1s gate and source voltages. a1s input filtering and roll-off are far slower than input frequen- cies of interest; its action does not interfere with the circuits main signal path. the 330pf capacitor prevents fast edges coupled through q2s collector base junction from influencing a1s operation. applicatio n s i n for m atio n wu u u q1 should contribute negligible timing error to minimize overall delay. figure 16s photo verifies q1s wideband operation. trace b, q1s source, lags the input (trace a) by only 300ps. input, fet buffer output and c1 output appear as traces a, b and c, respectively in figure 17. as before, the fet buffer is seen to contribute small timing error, and c1s output is about 8ns delayed from the input. + c1 lt1394 + a1 lt1097 10m 5v v trig 3v 0.01 f 0.1 f output 1394 f15 10k q2 2n3904 input 3v q1 2n5486 1.5k ?v 0.1 f 10m 100 330pf figure 15. buffer provides 2pf, 50pa input characteristics for fast trigger. amplifier-stabilized biasing eliminates fet offset 200ps/div 1394 f16 figure 16. trigger buffers 300ps delay minimizes timing error. 4ghz sampling oscilloscopes output is a series of dots a = 1v/div b = 1v/div figure 17. input (trace a), fet source (trace b) and output (trace c) waveforms for the trigger. total delay is 8ns 10ns/div 1394 f17 a = 1v/div b = 1v/div c = 2v/div
14 lt1394 high speed adaptive trigger circuit line and fibre-optic receivers often require an adaptive trigger to compensate for variations in signal amplitude and dc offsets. the circuit in figure 18 triggers on 2mv to 175mv signals from 100hz to 45mhz while operating from a single 5v rail. a1, operating at a gain of 15, provides wideband ac gain. the output of this stage biases a 2-way peak detector (q1 through q4). the maximum peak is stored in q2s emitter capacitor, while the minimum excur- sion is retained in q4s emitter capacitor. the dc value of the midpoint of a1s output signal appears at the junction of the 500pf capacitor and the 3m w units. this point always sits midway between the signals excursions, egardless of absolute amplitude. this signal-adaptive volt- age is buffered by a2 to set the trigger voltage at the lt1394s positive input. the lt1394s negative input is biased directly from a1s output. the lt1394s output, the circuits output, is unaffected by >85:1 signal amplitude variations. bandwidth limiting in a1 does not affect trigger- ing because the adaptive trigger threshold varies ratiometrically to maintain circuit output. applicatio n s i n for m atio n wu u u figure 19 shows operating waveforms at 45mhz. trace as input produces trace bs amplified output at a1. the comparators output is trace c. split supply versions of this circuit can achieve band- widths to 50mhz with wider input operating range. a = 0.1v/div b = 0.1v/div c = 5v/div 50ns/div an72 f64 figure 19. adaptive trigger responding to a 40mhz, 5mv input. input amplitude variations from 2mv to 175mv are accommodated 5v + a1 lt1227 + a2 lt1006 input 5v 5v 5v trigger out 1394 f18 500pf 0.1 f 510 470 470 750 36 1 3 2 4 14 13 15 5 6 12 10 11 2k 10 f 2k 2k + 0.1 f 0.1 f 0.005 f 0.005 f 100 f + q1, q2, q3, q4 = ca3096 array: tie substrate (pin 16) to ground = 1n4148 + lt1394 q1 q2 q3 q4 3m 3m figure 18. 45mhz single supply adaptive trigger. output comparators threshold varies ratiometrically with input amplitude, maintaining data integrity over > 85:1 input amplitude range
15 lt1394 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio n u dimensions in inches (millimeters) unless otherwise noted. s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 0996 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** msop (ms8) 1197 * dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.006" ( 0.152mm ) per side 0.021 0.006 (0.53 0.015) 0 ?6 typ seating plane 0.007 (0.18) 0.040 0.006 (1.02 0.15) 0.012 (0.30) ref 0.006 0.004 (0.15 0.102) 0.034 0.004 (0.86 0.102) 0.0256 (0.65) typ 12 3 4 0.192 0.004 (4.88 0.10) 8 7 6 5 0.118 0.004* (3.00 0.102) 0.118 0.004** (3.00 0.102) ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660)
16 lt1394 1394f lt/tp 0499 4k ? printed in usa ? linear technology corporation 1998 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com typical applicatio n u voltage-controlled crystal oscillator (vcxo) figure 20, a variant of the basic crystal oscillator, permits voltage tuning the output frequency. such voltage-con- trolled crystal oscillators (vcxo) are often employed where slight variation of a stable carrier is required. this example is specifically intended to provide a 4 ntsc sub-carrier tunable oscillator suitable for phase locking. the lt1394 is set up as a crystal oscillator, operating similarly to figure 3 (a). the varactor diode is biased from the tuning input. the tuning network is arranged so a 0v to 5v drive provides a reasonably symmetric, broad tuning range around the 14.31818mhz center frequency. the indicated selected capacitor sets tuning bandwidth. it should be picked to complement loop response in phase locking applications. figure 21 is a plot of tuning input voltage versus frequency deviation. tuning deviation from the 4 ntsc 14.31818mhz center frequency exceeds 240ppm for a 0v to 5v input. part number description comments lt1016 ultrafast precision comparator industry standard 10ns comparator lt1116 12ns single supply ground-sensing comparator single supply version of lt1016 lt1671 fast single supply comparator 60ns, 450 m a single supply comparator lt1720 ultrafast dual single supply comparator dual 4.5ns, 4ma single supply comparator related parts figure 21. control voltage vs output frequency for figure 15. tuning deviation from center frequency exceeds 240ppm input voltage (v) 0 frequency deviation (khz) 2 4 5 9 8 7 6 5 4 3 2 1 0 1394 f21 13 14.314.0mhz 14.31818mhz 14.3217mhz figure 20. a 4 ntsc sub-carrier voltage-tunable crystal oscillator. tuning range and bandwidth accommodate variety of phase locked loops 1394 f20 + lt1394 5v 390 200pf * 1% film resistor ** northern engineering labs c-2350n-14.31818mhz *** c select sets tuning bandwidth. set to complement loop response in phase locking applications ? varactor diode 5v frequency output 3.9k* v in 0v to 5v 1m mv-209 ? 2k 2k 100pf 15pf y1** 100pf c select*** 0.047 f 1m 1m 1m* 1n4148 lt1004-2.5 47k* 1k*

▲Up To Search▲

Price & Availability of LT1394-15

	To Download LT1394-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .